Transistor structure and method for making same

ABSTRACT

A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to integrated circuit devices andmore specifically to field effect devices such as field effecttransistors (FET) for use in integrated circuits.

[0003] 2. Description of the Prior Art

[0004] In manufacturing transistors, re-oxidation has been used in 5 μmto 1.2 μm technologies to improve transistor lifetimes and gate oxidereliability due to higher fields occurring at the etched polysilicontransistor edges. For example, U.S. Pat. No. 4,553,314 teaches usingre-oxidation to manufacture semiconductor devices. Typically, 3 μm and 5μm technologies use re-oxidation thicknesses from about 1200 Å to about2500 Å depending on the particular device. In 1.5 μm and 2 μmtechnologies, re-oxidation thicknesses from about 500 Å to about 1,000 Åare used.

[0005] In 0.8 μm technology, however, the re-oxidation process has beendiscontinued because the lifetimes of transistors currently manufacturedwithout the re-oxidation process is better than with the re-oxidationprocess. Such a situation is caused by the formation of asperities onthe underside of the polysilicon layer of the transistor during there-oxidation process. These asperities are of little importance untilthe gate oxide thicknesses are reduced to below 200 Å as used insubmicron technology. At this point, the asperities become a contributorto the increased field at the transistor edge and of hot carrierinjection (HCI). These asperities are caused by (1) oxidant diffusionalong polysilicon grain boundaries creating single crystal siliconprotrusions and (2) oxide thicknesses under the polysilicon edgeincreasing during re-oxidation, causing polysilicon grain boundary slipto occur and creating multiple edges, which results in an overallincrease in angle geometries.

[0006] In addition, moving to device geometries below 0.8 μm technologyhas resulted in marginal lifetimes of the transistors. Thus, it isdesirable to have a gate structure that has an increased lifetime usingre-oxidation under the gate edge but without the asperities caused bypresently used re-oxidation processes.

SUMMARY OF THE INVENTION

[0007] The present invention is a gate structure in a transistor andmethod for fabricating the structure. A gate structure is formed on asubstrate. The gate structure includes three layers: an oxide layer, anitride layer and a polysilicon layer. The oxide layer is located on thesubstrate, the nitride layer is located on the oxide layer, and thepolysilicon layer is located on the nitride layer. The gate structure isreoxidized to form a layer of oxide over the gate structure. The nitridelayer prevents the formation of asperities on the underside of thepolysilicon layer during reoxidation of the transistor.

BRIEF DESCRIPTION-OF THE DRAWINGS

[0008] The novel features believed characteristic of the invention areset forth in the appended claims. The invention itself however, as wellas a preferred mode of use, and further objects and advantages thereof,will best be understood by reference to the following detaileddescription of an illustrative embodiment when read in conjunction withthe accompanying drawings, wherein:

[0009] FIGS. 1-4 illustrate cross-sections of a portion of asemiconductor device during fabrication;

[0010]FIG. 5 illustrates a cross-section of a semiconductor device;

[0011]FIG. 6 illustrates a semiconductor device after reoxidation;

[0012] FIGS. 7A-7C depict an enlarged view of the cross-section shown inFIG. 5;

[0013]FIG. 8 illustrates an enlarged view of a cross-section from FIG.6;

[0014] FIGS. 9-10 illustrate cross-sections of a portion of asemiconductor device during an implantation process;

[0015]FIG. 11 depicts a cross-section of a semiconductor device afterreoxidation and implantation of the source and drain regions; and

[0016]FIG. 12 is a graph of current injection for two semiconductordevices.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0017] The process steps and structures described below do not form acomplete process flow for manufacturing integrated circuits. The presentinvention can be practiced in conjunction with integrated circuitfabrication techniques currently used in the art, and only so much ofthe commonly practiced process steps are included as are necessary foran understanding of the present invention. The figures representingcross-sections of portions of an integrated circuit during fabricationare not drawn to scale, but instead are drawn so as to illustrate theimportant features of the invention.

[0018] The present invention allows for the use of re-oxidation toimprove transistor lifetimes by reducing fields in transistortechnologies through elimination of previous limitations. According tothe present invention, a structure is provided which uses the increaseddistance at the gate edge, but eliminates the asperities created duringre-oxidation so that re-oxidation may be used for submicrontechnologies. The structure of the present invention prevents theeffects of oxidation on the polysilicon gate by using a thin siliconnitride layer located between the polysilicon and the gate oxide in atransistor.

[0019] Referring now to FIG. 1, a schematic cross-section of asemiconductor device at an early stage in a manufacturing process isillustrated according to the present invention. Transistor 10 includes asubstrate 12, which is typically a monocrystalline silicon of aconventional crystal orientation known in the art. Many features of thepresent invention are applicable to devices employing semiconductormaterials other than silicon as will be appreciated by those of ordinaryskill in the art. Substrate 12 may be either a p-type substrate or ann-type substrate. In the present illustrative example, a p-typesubstrate is employed. As can be seen with reference to FIG. 1, fieldoxides 14 a and 14 b have already been created in transistor 10.

[0020] In FIG. 2, oxide layer 16, also called an insulating oxide layeror a gate oxide layer, is grown on surface 18 of substrate 12 intransistor 10. Thereafter, in FIG. 3, a silicon nitride layer 20 isdeposited on top of oxide layer 16 and field oxide 14 a and 14 b.Silicon nitride layer 20 is deposited on transistor 10 in a layer thatis preferably from about 10 Å to about 50 Å thick according to thepresent invention.

[0021] Thereafter, a polycrystalline silicon (polysilicon) layer 22 isdeposited over silicon nitride layer 20 as illustrated in FIG. 4.Alternatively, a refractory metal, such as Mo, Ta, or W, or a metalsilicide, such as MoSi₂ TaSi₂ or WSi₂, may be used. Transistor 10 isthen patterned and etched to expose surface 18 in selected portions oftransistor 10 as illustrated in FIG. 5 wherein a gate structure 21 fortransistor 10 is formed. Next, re-oxidation is performed to produceoxide layer 26 covering the gate structure and the substrate, asillustrated in FIG. 6. Typically, in reoxidation, the exposed substrateand the gate structure are exposed to any oxidizing ambient. Such aprocess is well known to those skilled in the art. Also, oxide layer 26produced by reoxidation is preferably from about 25 Å to about 500 Åthick on the p-type substrate.

[0022] Referring now to FIG. 7, an enlarged view of a representativeportion of FIG. 5 is depicted. The figure shows in greater detail aportion of gate 21. As can be seen, polysilicon layer 22, nitride layer20, and oxide layer 16 have been etched away to expose surface 18 ofsubstrate 12. Alternatively, oxide layer 16 may be left in its entiretyas illustrated in FIG. 7B, or partially etched away as illustrated inFIG. 7C.

[0023] Now referring to FIG. 8, an enlarged view of transistor 10 fromFIG. 6 is depicted. This enlarged view shows oxide layer 26 as grownduring reoxidation of transistor 10. The reoxidation process whichresults in the growth of oxide layer 26 has the effect of movingperipheral edge 40 of polysilicon layer 22 in gate structure 21, asillustrated in FIG. 8. The position of the peripheral edge of gatestructure 21 in polysilicon layer 22 is indicated by the dashed line40′. In addition, the growth of oxide layer 26 moves surface 18 downwardfrom its original position 18′ to form an indentation 19 (the section ofoxide from original position 18′ to surface 18) in surface 18 ofsubstrate 12 near the peripheral edge of gate structure 21. Also,nitride layer 20 has an uplift 20 a caused by reoxidation of thetransistor.

[0024] The reoxidation process is well to those skilled in the art.Various temperatures and times may be may be used depending on theoxidizing ambient employed. For example, the transistor may be exposedto an oxidizing ambient such as dilute steam at a temperature from about650° C. to about 900° C. from about 10 minutes to about 60 minutes.

[0025] Nitride layer 20 acts as a protective layer and prevents theformation of asperities in polysilicon layer 22 in gate structure 21during reoxidation. Nitride layer 20 prevents oxidation of the bottomside of the polysilicon layer 22 and prevents formation of geometrieswhich result in increased electric fields. In addition, the nitridelayer will prevent outdiffusion of polysilicon dopants into the gateoxide, which if excessive can lead to early gate break downs. Such afeature is important especially when polysilicon dopants such as boronare used in large amounts. Moreover the higher density silicon nitrideincreases resistance of the gate oxide to physical damage during postgate oxide and polysilicon deposition silicidations.

[0026] Although the process depicted in FIGS. 1-4 deposits siliconnitride onto the gate oxide layer, other processes may be employed tocreate a silicon nitride layer between gate oxide layer 16 and thepolysilicon layer 22. For example, a nitrogen (N₂) implant into thepolysilicon followed by annealing the device forms a thin siliconnitride layer at the polysilicon oxide interface. More information onforming thin silicon nitride layers may be found in an article byJosquih et al., “The Oxidation Inhibition in Nitrogen ImplantedSilicon”, J. Electrochem. Soc: SOLID-STATE SCIENCE AND TECHNOLOGY(August 1982) pp. 1803-1811 and in U.S. Pat. No. 5,250,456.

[0027] When nitrogen implantation is used to form a silicon nitridelayer, polysilicon layer 22 is deposited over oxide layer 16 asillustrated in FIG. 9. Thereafter, nitrogen ions are implanted intotransistor 10 as illustrated in FIG. 10. In accordance with a preferredembodiment of the present invention, ¹⁵N₂+ at a dose in the range ofabout 1E14 to 1E16 ions/cm². Thereafter, transistor 10 is annealed at atemperature from about 800° C. to about 1100° C. inert ambient gas, suchas argon or helium, for about 15 minutes to 60 minutes. As a result, anitride layer 20 as illustrated in FIG. 4 results from the annealingprocess. Nitride layer 20 is formed in a layer from about 15 Å to about20 Å thick. Alternatively, transistor 10 may be annealed using rapidthermal processing in an inert ambient gas at about 900° C. to about1200° C. for a period of time from about 5 seconds to about 3 minutes.

[0028] The anneal of the nitrogen-implanted polysilicon overlying oxidelayer 16 causes the implanted nitrogen to accumulate at thepolysilicon/oxide interface, forming a nitride layer. Thereafter,transistor 10 is patterned and etched as illustrated in FIG. 5 andre-oxidized as shown in FIG. 6.

[0029] Alternatively, silicon nitride layer 20 may be formed on top ofoxide layer 16, as illustrated in FIG. 3, using a rapid thermal annealprocess. For example, N₂ or NH₃ may be employed in a rapid thermalanneal process at a temperature from about 700° C. to about 1200° C. fora period of time from about 10 seconds to about 300 seconds to form asilicon nitride layer.

[0030] Implantation to produce source and drains for transistor 10 mayperformed after the re-oxidation procedure as illustrated in FIG. 11.For example, n-type impurities may be implanted into a p-type substrate.The source/drain regions 30 a and 30 b are n-type active regions.Lightly doped drain (LDD) regions 32 a and 32 b are defined usingsidewall oxide spacers 36 a and 36 b as known by those skilled in theart. The processing employed to produce the additional structuresdescribed in FIG. 10 after reoxidation are well known to those skilledin the art. Alternatively, LDDs 32 a and 32 b and sidewall spacers 36 aand 36 b may be omitted according to the present invention.

[0031] Referring now to FIG. 12, a graph of current injection for twosemiconductor devices is depicted. The graph is of injection current,IG, for different voltages. IG currents for a first semiconductorwithout a nitride layer located between the polysilicon gate and thegate oxide is represented by line 1. IG currents for a secondsemiconductor device including a nitride layer between the polysiliconand gate oxide is represented by line 2. As can be seen from the graphin FIG. 12, the early rise currents are reduced in line 2. The twosemiconductor devices are both n-channel transistors with oxide spacers.The two devices have a 0.7 μm wide gate finger structure and area ofabout 2e⁴ μm². Both devices under went reoxidation using 15 O₂ at 800°C. The second device has a nitride layer that is 10 Å. Otherwise thefirst and second devices are substantially identical. The nitride layerin the second semiconductor device represented in line 2 was created bysilicon nitride deposition using a 30 minute deposition time at 750° C.The second semiconductor device was exposed to dichlorosilane (SiCl₂H₂)and ammonia (NH₃) in a ratio of 1 part dichlorosilane to 10 partsammonia.

[0032] While the invention has been particularly shown and describedwith reference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

What is claimed is:
 1. A method for fabricating a portion of asemiconductor device comprising: forming a gate structure on asubstrate, the gate structure including an insulating oxide layer, anitride layer and a polysilicon layer, wherein the oxide layer islocated on the substrate, the nitride layer is located on the oxidelayer, and the polysilicon layer is located on the nitride layer; andreoxidizing the gate structure to form a layer of oxide over the gatestructure.
 2. The method of claim 1, wherein said forming stepcomprises: depositing the insulating oxide layer on the substrate;depositing the polysilicon layer on the oxide layer; implanting nitrogenions into the layers; and annealing the layers to form a nitride layerbetween the oxide layer and the polysilicon layer.
 3. The method ofclaim 2, wherein the implanting step includes implanting nitrogen ionsinto the layers at a dose from about 1E14 ions/cm² to about 1E16ions/cm².
 4. The method of claim 2, wherein the annealing step includesannealing the layers in an inert ambient gas at a temperature from about800° C. to about 1100° C.
 5. The method of claim 2, wherein theannealing step includes annealing the layers in an inert ambient gas ata temperature from about 900° C. to about 1200° C. using a rapid thermalprocess.
 6. The method of claim 2, wherein the annealing step includesannealing the layers for about 15 minutes to about 60 minutes.
 7. Themethod of claim 2, wherein the annealing step forms a nitride layer fromabout 10 Å to about 50 Å thick.
 8. The method of claim 2, wherein thereoxidizing step includes reoxidizing the gate structure to form anoxide layer from about 25 Å to about 500 Å thick.
 9. The method of claim2, wherein prior to the reoxidizing step, forming source and drainregions in the substrate.
 10. The method of claim 2, wherein theimplanting step includes implanting nitrogen ions into the layers at adose from about 1E14 ions/cm² to about 1E16 ions/cm².
 11. The method ofclaim 10, wherein the annealing step includes annealing the layers forabout 15 minutes to about 60 minutes.
 12. The method of claim 11,wherein the annealing step further includes annealing the layers in aninert ambient gas at a temperature from about 800° C. to about 1100° C.13. The method of claim 11, wherein the annealing step further includesannealing the layers using rapid thermal processing in an inert ambientgas at a temperature from about 900° C. to about 1200° C. using a rapidthermal process.
 14. The method of claim 13, wherein the inert ambientgas is argon.
 15. The method of claim 13, wherein the implanting stepincludes implanting ¹⁵N₂+ nitrogen ions.
 16. The method of claim 15,wherein the reoxidizing step includes reoxidizing the gate structure forform a oxide layer from about 25 Å to about 500 Å thick.
 17. The methodof claim 1, wherein said forming step comprises: depositing theinsulating oxide layer on the substrate; depositing the nitride layer onthe oxide layer; depositing the polysilicon layer on the nitride layer.18. The method of claim 17, wherein the depositing step includesdepositing nitride layer on the insulating oxide layer to a thicknessfrom about 10 Å to about 50 Å.
 19. The method of claim 17, wherein thereoxidizing step includes reoxidizing the gate structure to form anoxide layer from about 25 Å to about 500 Å thick.
 20. The method ofclaim 17, wherein the step of forming a gate structure further includesselectively etching away portions of the insulating oxide, nitride, andpolysilicon layers to expose substrate and form a peripheral edge aroundthe gate structure; and wherein the reoxidizing step comprises exposingthe substrate to an oxidizing ambient to oxidize the exposed substrate.21. The method of claim 20, wherein the exposing step causes an upliftin a peripheral portion of the nitride layer.
 22. The method of claim20, wherein the exposing step causes an indentation in the substratenear a peripheral edge of the gate structure.
 23. The method of claim17, wherein prior to the reoxidizing step, forming source and drainregions in the substrate.
 24. A method for fabricating a portion of asemiconductor device comprising: forming an oxide gate layer on asurface of a substrate; forming a nitride layer on the oxide gate layer;forming a polysilicon layer on the nitride layer; etching away thepolysilicon and nitride layers in selected areas to form a gatestructure; and reoxidizing the gate structure to form a layer of oxide.25. The method of claim 24, wherein the step of forming a nitride layercomprises depositing a nitride layer on the oxide gate layer.
 26. Themethod of claim 24, wherein the step of forming a nitride layercomprises forming a nitride layer of about 10 Å to about 50 Å thick onthe oxide gate layer.
 27. The method of claim 24, wherein the step ofreoxidizing the exposed substrate comprises reoxidizing the reoxidizingthe exposed substrate to form an oxide layer from about 25 Å to about500 Å thick.
 28. The method of claim 24, wherein the step of etchingexposes the surface of the substrate; and wherein the step ofreoxidizing the exposed substrate comprises exposing the substrate to anoxidizing ambient to oxidize the exposed substrate surface.
 29. Themethod of claim 28, wherein the exposing step causes an uplift in aportion of the nitride layer proximate to a peripheral edge of the gatestructure.
 30. The method of claim 28, wherein the exposing stepincludes exposing the substrate to the oxidizing ambient at atemperature from about 650° C. to about 900° C.
 31. The method of claim29, wherein the exposing step further includes exposing the substrate tothe oxidizing ambient for about 10 minutes to about 60 minutes.
 32. Themethod of claim 24, wherein prior to the reoxidizing step, formingsource and drain regions in the substrate.
 33. The method of claim 24,further comprising forming source and drain regions in the substrateafter the reoxidizing step.
 34. A method for fabricating a portion of asemiconductor device comprising: forming an oxide layer on a substrate;forming a polysilicon layer on the oxide layer; implanting a nitrogenion into the oxide and polysilicon layers; annealing the oxide andpolysilicon layers to form a nitride layer between the oxide andpolysilicon layers; etching the polysilicon, nitride, and oxide layersto expose the substrate and form a gate structure; and reoxidizing theexposed substrate and the gate structure.
 35. The method of claim 34,wherein the implanting step includes implanting nitrogen ions into thelayers at a dose from about 1E14 ions/cm² to about 1E16 ions/cm². 36.The method of claim 34, wherein the implanting step includes implanting¹⁵N₂+ nitrogen ions into the layers.
 37. The method of claim 34, whereinthe annealing step further includes annealing the layers in an inertambient gas at a temperature from about 800° C. to about 1100° C. 38.The method of claim 34, wherein the annealing step further includesannealing the layers using rapid thermal processing in an inert ambientgas at a temperature from about 900° C. to about 1200° C.
 39. The methodof claim 34, wherein the annealing step includes annealing the layersfor about 15 minutes to about 60 minutes.
 40. The method of claim 34,wherein the annealing step forms a nitride layer from about 10 Å toabout 50 Å thick
 41. The method of claim 34, wherein the etching stepfurther includes creating a peripheral edge around the gate structure.42. The method of claim 41, wherein the step of reoxidizing the exposedsubstrate comprises exposing the substrate to an oxidizing ambient tooxidize the exposed substrate.
 43. The method of claim 42, wherein theexposing step causes an uplift in a portion of the nitride layerproximate to the peripheral edge.
 44. The method of claim 34, whereinprior to the reoxidizing step, forming source and drain regions in thesubstrate.
 45. The method of claim 34, further comprising forming sourceand drain regions in the substrate after the reoxidizing step.
 46. Anintegrated circuit device comprising: a substrate; a gate structure,wherein the gate structure includes: a gate oxide layer on thesubstrate, a nitride layer on the gate oxide layer, and a polysiliconlayer over the nitride layer; a channel region under the gate structure;and source/drain regions in the substrate adjacent the channel region.47. The integrated circuit device of claim 46, wherein the nitride layeris from about 10 Å to about 50 Å thick.
 48. The integrated circuitdevice of claim 46, wherein the nitride layer is deposited over saidgate oxide layer.
 49. The integrated circuit device of claim 46, whereinthe nitride layer is formed by nitrogen implantation to form animplanted area and by annealing of the implanted area.
 50. Theintegrated circuit device of claim 46, wherein the gate has a peripheraledge and further including an uplift in the nitride layer occurring inportions of the nitride layer proximate the peripheral edge of the gatestructure, the uplift caused by reoxidation of the gate structure,wherein asperities are absent from the polysilicon layer.
 51. Theintegrated circuit device of claim 46, wherein the substrate has asurface and further including an indentation in the surface of thesubstrate located proximate to the peripheral edge of the gate, theindentation resulting from reoxidation of the integrated circuit device.52. The integrated circuit device of claim 46 further wherein the gatestructure includes sidewall spacers located on each edge of the gatestructure and lightly doped drain regions in the substrate located inthe substrate below the sidewall spacers.
 53. The integrated circuitdevice of claim 46, wherein the substrate is a p-type substrate andwherein the source/drain regions are formed by implanting n-typeimpurities in the p-type substrate.
 54. The integrated circuit device ofclaim 53, wherein the source/drain regions are implanted prior toreoxidation.
 55. The integrated circuit device of claim 53, wherein thesource/drain regions are implanted after oxidation.